Synopsys Design Compiler Tutorial 2021

# Create clock on port 'clk' create_clock -name "core_clk" -period 2.0 [get_ports clk] set_clock_uncertainty -setup 0.050 [get_clocks core_clk] set_clock_uncertainty -hold 0.050 [get_clocks core_clk] Latency (network + source) set_clock_latency -source -max 0.200 [get_clocks core_clk] set_clock_latency -max 0.100 [get_clocks core_clk] Transition (slew rate on the clock tree) set_clock_transition -max 0.080 [get_clocks core_clk] 4.2 Input & Output Delays # Input path: data arrives 0.6ns after clock edge set_input_delay -max 0.6 -clock core_clk [get_ports din*] set_input_delay -min 0.1 -clock core_clk [get_ports din*] Output path: data must be valid 0.5ns before next clock set_output_delay -max 0.5 -clock core_clk [get_ports dout*] set_output_delay -min 0.1 -clock core_clk [get_ports dout*] Load capacitance (typical for 2021: 0.05pF) set_load 0.05 [get_ports dout*] set_driving_cell -lib_cell BUFFD2 [get_ports din*] 4.3 Area and Power (2021 Focus) # Don't optimize area beyond 95% of initial estimate set_max_area 0 For 2021 low-power flow (UPF) load_upf -scope . ./design.upf set_power_optimization -low_power_mode Part 5: The Synthesis Strategy (Compile) DC 2021 primarily uses compile_ultra for high-performance designs. This enables advanced features like auto-ungrouping, logic restructuring, and datapath optimization. Basic Compile Flow: # Set operating conditions (worst case for setup) set_operating_conditions -max "WCCOM" -max_library $target_library Mapping effort: high, medium, low set compile_ultra_ungroup_dw false # Keep datapath elements grouped Start synthesis echo "Starting compile_ultra at [date]" compile_ultra -timing_high_effort -area_high_effort echo "Synthesis finished at [date]"

# Read top-level Verilog read_verilog ./rtl/cpu.v ./rtl/alu.v ./rtl/regfile.v read_vhdl -library work ./rtl/cpu.vhd Link the design (resolve references) current_design $DESIGN_NAME link synopsys design compiler tutorial 2021

After compile_ultra , run a quick incremental pass to fix remaining violations. # Create clock on port 'clk' create_clock -name