| Parameter | Value | | :--- | :--- | | | Programmable Sound Generator (PSG) | | Package | 28-pin DIP (Dual Inline Package) or SOP | | Technology | CMOS (Low power consumption) | | Channels | 3 independent tone channels | | Noise Generator | 1 shared pseudo-random noise source | | Envelope Generator | 1 programmable envelope (can be cycled or single-shot) | | Output | 3-bit D/A converter (digital output, usually via external resistor ladder) | | Clock Frequency | Up to 2 MHz (some clones support up to 4 MHz) | | Supply Voltage (Vdd) | 5V ±10% | | Current Consumption | < 25 mA (typical), < 250 µA (standby) |
| /BC1 | /BDIR | Mode | Operation | | :--- | :--- | :--- | :--- | | 0 | 0 | Inactive | Data bus high impedance | | 0 | 1 | Write | Write data from DA0-7 to the selected register (address from A8) | | 1 | 0 | Read | Read value from selected register | | 1 | 1 | Address | Latch address from A8, prepare for read/write |
Whether you are restoring a vintage arcade board, building a chiptune synthesizer, or simply learning about retro sound hardware, the KC89C72 remains a rewarding component. Use this guide as your companion to the official datasheet, and you will navigate its registers, timing, and audio output with confidence. kc89c72 datasheet
| Register (A8 = 0-15) | Name | Function | | :--- | :--- | :--- | | 0 | Channel A Fine Tune | Lower 8 bits of tone period | | 1 | Channel A Coarse Tune | Upper 4 bits of tone period | | 2 | Channel B Fine Tune | Lower 8 bits | | 3 | Channel B Coarse Tune | Upper 4 bits | | 4 | Channel C Fine Tune | Lower 8 bits | | 5 | Channel C Coarse Tune | Upper 4 bits | | 6 | Noise Period | 5-bit noise frequency control | | 7 | Mixer / I/O Enable | Enable/disable tone/noise per channel, I/O control | | 8 | Channel A Volume | 4-bit volume (or envelope enable) | | 9 | Channel B Volume | Same as above | | 10 | Channel C Volume | Same as above | | 11 | Envelope Fine | Lower 8 bits of envelope period | | 12 | Envelope Coarse | Upper 8 bits (total 16-bit envelope period) | | 13 | Envelope Shape | Cycle, hold, alternate, attack patterns | | 14 | I/O Port A | Not used on KC89C72 (read returns 0xFF) | | 15 | I/O Port B | Not used |
void setup() // Set pins as outputs... // Reset the chip digitalWrite(RESET_PIN, LOW); delay(10); digitalWrite(RESET_PIN, HIGH); | Parameter | Value | | :--- |
On the KC89C72, pins 25 and 26 (/IOA, /IOB) are not functional as general-purpose I/O (unlike the AY-3-8910). Pull them to Vdd through 10k resistors. Part 3: Bus Control Logic (How to Read/Write Registers) Unlike modern I2C/SPI devices, the KC89C72 uses a simple 3-line control bus: /BDIR, /BC1, and /BC2 . These three signals determine the bus cycle.
By the end of this guide, you will have all the critical information found in an official datasheet, plus practical application notes, timing diagrams, and code examples. Before diving into the pin configuration, let's highlight the core specifications that define the KC89C72. These three signals determine the bus cycle
This article serves as a deep-dive datasheet analysis and application guide. The KC89C72 is a CMOS (Complementary Metal-Oxide-Semiconductor) version of the classic AY-3-8912 (a 28-pin shrink DIP variant of the 40-pin AY-3-8910). It is a Programmable Sound Generator (PSG) capable of producing three independent square-wave tones, an envelope generator, and a noise source.